This invention relates to the lithographic production of integrated circuits and, in particular, to a method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer.
The integrated circuit fabrication process consists of a series of steps which begins with an input set of geometries or configurations of integrated circuit patterns provided by the very large scale integration (VLSI) designer and results in a manufactured integrated circuit chip consisting of devices and interconnects which perform a needed function. Exposure tools print the integrated circuit patterns by lithographic methods on successive layers of a semiconductor wafer. These lithographic methods are well known and include using a photo mask to project the image of the circuit portion onto a resist layer, developing the resist layer, removing portions of the resist layer to recreate the circuit portion image on the wafer layer, and then etching and depositing desired circuit materials on or in the wafer layer. The exposure tools achieve registration of each integrated circuit pattern among different pattern layers by aligning the integrated circuit portion on a current layer to an integrated circuit portion on a previously patterned layer. Precise control is important to minimize alignment and overlay error of the integrated circuit portions between circuit layers made by a lithographic process.
Each step in the manufacturing process introduces a certain amount of error, which causes the final resulting manufactured chip pattern design to deviate somewhat from that originally provided by the designer. Some of the places where errors are introduced are: 1) imperfections in the physical realization of the photo mask, 2) shape image distortion in the lithographic process used to expose wafers, 3) variations in the process across a single chip and/or wafer, 4) variations in the process from wafer to wafer, and 5) misalignment of photo masks from adjacent layers (overlay error).
In some cases, extra steps in the process are added in order to compensate for these imperfections. Examples include optical proximity correction, selective line-width biasing and the addition of line-end anchor shapes. In other cases, the imperfections lead to some conservatism in the design process. The usual embodiment of this conservatism is in the values associated with the design rules, which state what the minimum widths, spacings, and overlaps are for designs created in a given technology. Since the design rules are the primary vehicle for communicating the capabilities of the process from the technology developers to the chip designers, the rules must be set to values that can produce a reasonable yield for all possible geometries or configurations under all possible process conditions in consideration of all of the potential sources of error.
In reality, however, certain geometries or configurations or circuit portions are much more susceptible to failure than others. For example, it is well known that corners tend to round, and line-ends tend to shorten. Additionally, the importance of each of these imperfections varies greatly with the intended purpose of the particular geometry. For example, if a line end of a metal shape foreshortens, it is likely of little concern if there is no via in the vicinity of the foreshortening. However, the same foreshortening becomes of greater concern if that foreshortening, combined with other process imperfections, causes the amount of overlap with a neighboring via to be less than that necessary to provide a reliable electrical connection to the adjacent layer of metal.
In determining the design rule values for a particular technology, current techniques consist of a monte-carlo simulation of simple geometric shapes in simple geometric configurations. Simplistic rule-based assumptions are made about issues such as corner rounding and line-end foreshortening, and then the shapes are offset randomly in order to simulate overlay error. Because the geometries must remain simple in order to apply the simplistic rule-based assumptions, accurate results are only obtained for a simplistic set of geometries, and not the full set of geometries and shape configurations that can be seen in a typical VLSI design.
Once provided with a set of layout rules, the designer proceeds to produce a circuit layout based upon those rules which implement the intended functionality of the circuit, unit or chip. Since the designer has knowledge that different geometric configurations of shapes can result in different on-wafer images, he may be inclined to do a small amount of model-based simulation on areas of his design that he deems to be particularly critical, and that he predicts may be susceptible to failure. Such simulations are performed under a single set of process conditions with no good method for incorporating overlay error. These methods also require the layout designer to have good insights into those areas that are susceptible to failure.
In certain cases, in order to achieve an especially tight layout, a designer may intentionally violate certain layout rules. In these circumstances, he requests a waiver to the design rules for his particular geometric configuration of shapes from the waiver review board for the particular technology. Typically, the waiver granting determination is based upon the extensive experience of the collective members of the board, in some instances along with a small amount of process simulation performed on the particular geometries.
In each one of these areas, the vast complexity involved with the geometric configurations that can or do occur leads to inaccuracies, usually leading to overly conservative design geometries.